1. Field of the Invention
The present invention relates generally to data processing methods and systems, and more particularly, to methods and apparatus for examining multiple matched addresses associated with a storage device, such as a content addressable memory.
2. State of the Art
Presently, devices are known which are used to store data in conjunction with data processing systems. One such device is a content addressable memory (CAM), such as that described in U.S. Pat. No. 5,267,190 (Easley et al) and in U.S. Pat. No. 5,220,526 (Giles et al), the disclosures of which are hereby incorporated by reference in their entireties. As described in the '190 patent, a content addressable memory is a storage device which includes plural address registers, each of which holds a data word referred to therein as a "compare address". Further, the content addressable memory includes a write circuit which selectively loads compare addresses into the address registers. Input terminals are provided for supplying an address to be searched (i.e., "a search address") to the content addressable memory so that the search address can be compared with the compare addresses stored in the content addressable memory. To this end, compare circuits are coupled to each of the address registers and to the search address input terminals. In operation, if a search address which has been input via the search address input terminals corresponds to any of the compare addresses included in the plural address registers, a "match" signal is generated to indicate which of the address registers caused the match.
Typically, where a "match" signal is produced, it is used to address and read data stored in a separate register, such as a cache. Alternately, if no "match" signal is detected, then the content addressable memory and the cache are updated via a write operation.
Conventional content addressable memories are known which handle a situation wherein multiple matches are detected for a given search address. However, these conventional content addressable memories only identify an address of a single match (i.e., either the highest matched data/address, or the lowest matched data/address). As such, these content addressable memories do not permit the user to exploit multiple matched data/addresses to determine what, if any action should be taken. Rather, these memories are controlled in a manner which avoids the storing of multiple matched addresses therein, so that each search address corresponds to, at most, a single previously stored address of the content addressable memory.
For example, the '526 patent includes match line signals which are asserted when information to be written into a predetermined row of registers in the content addressable memory is identical to information previously stored in the content addressable memory (i.e., in another row of registers in the content addressable memory). Any asserted match line signal which was not disabled, indicates to the user when a search address is identical to a previously stored address of the content addressable memory. However, the user must activate each individual signal line (i.e., each of the "word x" lines) to determine if a match occurred for each given word address. As such, the technique for sequencing through multiple matched data/addresses is awkward and time consuming. For example, with a content addressable memory having 4,096 possible addresses, a situation where matches occurred at address locations 0 and 4,095 would be a worst case scenario. In this scenario, the user would be required to process each of the 4,096 addresses to isolate the multiple detected matches. As the size of the memory is increased, the number of addresses which must be processed will also increase.
Moreover, conventional content addressable memories which accommodate the identification of multiple matches involve the use of external logic (i.e., external to the integrated circuit on which the content addressable memory is formed). Further, processing contents of the memory can result in a modification of the memory output that can only be corrected by completely reloading the memory. For example, in the '526 patent, a match line signal associated with a predetermined row is disabled by a predetermined transistor when the row is written. As such, where an error occurs in reading and analyzing multiple matches of the memory, the entire memory must be rewritten.
Accordingly, it would be desirable to provide a storage device, such as a content addressable memory, which enables a user to individually examine and exploit the storage of multiple matches in a multiple match cycle via a simple and time efficient manner.